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Wednesday, December 5 • 3:35pm - 4:00pm
Reprogrammable Packet Processing Pipeline in FPGA for OVS Offloading

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Today’s cloud service providers want to see their CPU assets freed up from running network infrastructure software, resulting in demand for HW offloading of infrastructure components such as OVS. One key component for such an offload is a packet processing pipeline that parses, classifies, modifies and schedules packets efficiently. In addition, as the network requirements change, or new protocols emerge, the pipeline has to be reprogrammed while traffic is still flowing. This talk will focus on how we built such a pipeline inside an Intel Arria 10 FPGA. The pipeline can be reprogrammed by editing its definition in a language such as P4 or eBPF, which is then translated into hardware command tables that can be updated without interrupting the flow of traffic through the device. The SW programming and debugging tools around the pipeline will also be discussed.



Wednesday December 5, 2018 3:35pm - 4:00pm
Club Auto Sport, San Jose

Attendees (1)